1. Field of Invention
The present invention relates to an integrated circuit structure and its manufacturing method. More particularly, the present invention relates to the structure and manufacturing method of a dynamic random access memory (DRAM) capacitor.
2. Description of Related Art
As microprocessors become more powerful and the amount of computation capable of being processed by software programs increases, required memory capacity increases correspondingly. Following the increase in level of integration of DRAM devices, a memory cell now comprises a transfer field effect transistor (TFET) and a storage capacitor, only.
FIG. 1 is an equivalent circuit diagram of a DRAM cell. As shown in FIG. 1, when one of the capacitors C in an array of capacitors on a semiconductor substrate is selected, the charging state of the capacitor C can be used for storing a bit of data. Normally, a single bit is stored in a capacitor in a binary system. When the capacitor C is free of charge, logic "0" is implied, whereas when the capacitor is fully charged, logic "1" is implied.
In general, a dielectric layer 102 is deposited between the upper electrode (cell electrode) 101 and the lower electrode (storage electrode) 100 of the capacitor C providing the necessary dielectric constant. Furthermore, the capacitor C is electrically coupled to a bit line BL, and read/write operations are carried out by charging/discharging the capacitor C. The transfer field effect transistor T is a switch for carrying out the necessary charging or discharging of the capacitor C.
The transistor T is able to function as a switch because the bit line BL is connected to the source terminal of transistor T while the drain terminal of transistor T is connected to the capacitor C. In addition, a word line WL is connected to the gate terminal of the transistor T so that a control signal can be sent to turn on or off the connection from the bit line BL to the capacitor C.
For DRAM having a storage capacity less than 1M (1 Megabit), two-dimensional capacitors commonly known as planar type capacitors are generally formed in integrated circuits. Since a planar type capacitor occupies vast semiconductor substrate area, it is not suitable for forming highly integrated circuits. Therefore, three-dimensional capacitors are used in almost every highly integrated circuit, such as memory with a storage capacitor bigger than 4M. In general, three-dimensional capacitors can be classified roughly into a stacked type or a trench type.
Compared with a planar type of capacitor, a stacked or trench capacitor is capable of providing a relatively large capacitance even when the size of a memory cell is further shrunk. However, when the level of memory device integration is further reduced, for example, DRAM having memory capacity greater than 64K, simple three-dimensional structures are still incapable of providing the necessary capacitance.
As size of each memory cell decreases, capacitance of its storage capacitor will also decrease. When the capacitance of a capacitor decreases, probability of soft errors caused by .alpha.-ray increases accordingly.
One method of increasing overall surface area of a capacitor and hence its capacitance is to allow the electrode and dielectric thin film to extend horizontally and to stack them one after another, thereby forming a fin-type stacked capacitor.
A second method of increasing overall surface area of a capacitor and hence its capacitance is to allow the electrode and dielectric thin film to extend vertically upward, thereby forming a cylindrical-type stacked capacitor structure.
As the level of integration continues to increase, the dimensions of each DRAM cell have to be reduced. Consequently, new storage capacitor structures and manufacturing methods capable of maintaining a constant capacitance despite a reduction in occupied area are being sought rigorously.
FIGS. 2A through 2E are cross-sectional views showing the progression of manufacturing steps in fabricating a dual cylinder capacitor according to a conventional method. First, as shown in FIG. 2A, an isolating field oxide layer 202, conductive structures 204, insulating layers 206 and polysilicon layer 208 are formed over a substrate 200. Next, silicon oxide is deposited over the substrate 200, and then the silicon oxide layer is patterned with a mask to form an oxide layer 210 having an opening that exposes a portion of the polysilicon layer 208.
Thereafter, as shown in FIG. 2B, silicon nitride is deposited and then etched to form silicon nitride spacers 212 on the sidewalls of silicon oxide layer 210 on either side of the opening. Next, the exposed polysilicon layer 208 is oxidized using a thermal oxidation process so that a grainy oxide isolation layer 214 is formed in the narrow regions between the spacers 212.
Subsequently, as shown in FIG. 2C, the silicon nitride spacers 212 are removed. Then, using the silicon oxide layer 210 and the oxide isolation layer 214 as masks, the polysilicon layer 208 is etched to form a polysilicon layer 208a having a number of trenches.
Next, as shown in FIG. 2D, the silicon oxide layer 210 and the oxide isolation layer 214 are removed. Thereafter, photolithographic and etching operations are used to remove a portion of the polysilicon layer 208a in the peripheral region in order to form a dual cylinder-shaped lower electrode structure 208b. Through carving out trenches in the polysilicon layer, additional surface area is obtained for the lower electrode 208b.
However, in the process of forming the lower electrode structure, photolithographic and etching operations have to be conducted when the opening is formed in the silicon oxide layer 210. Furthermore, more photolithographic and etching operations also have to be carried out when the neighboring lower electrode structures 208b are isolated. Therefore, if there is deviation in the above two photolithographic and etching operations, the peripheral structure of the dual cylinder electrode will have non-uniform width. The narrower side 216, shown in FIG. 2E, can easily break during subsequent processing operations and may lead to undesirable device properties.
In light of the foregoing, there is a need an improved method of fabricating dual cylinder electrodes.